The present invention relates to a processor, such as a microprocessor or a signal processor, and more particularly to a technique the processor uses for executing data transfer instructions.
FIG. 11 shows an example of a prior art microprocessor.
The microprocessor shown in FIG. 11 comprises a program counter 1, an instruction memory 2, an instruction decoder 3, a data memory 4, a register file 5, an operation circuit 6, an accumulator 7, and a flag register 8.
The program counter 1 outputs an address signal P.
This address signal P is supplied to the address signal input terminal of the instruction memory 2. In response to this, an instruction Q stored at the address area corresponding to the address signal P is read out from the instruction memory 2 and is written in an instruction register IR (not shown).
The instruction Q stored in the instruction register IR is supplied to the instruction input terminal of the instruction decoder 3. Upon receipt of the instruction Q, the instruction decoder 3 analyzes it and generates signals corresponding thereto. To be more specific, control signals g, h, i, j and k are generated, and supplied to the data memory 4, register file 5, operation circuit 6, program counter 1 and instruction memory 2, respectively.
The data input/output terminals of the data memory 4, register file 5 and operation circuit 6 are connected to a data bus. By way of this data bus, data D is exchanged among the data memory 4, register file 5 and operation circuit 6.
The operation circuit 6 executes an arithmetic operation in response to data A' stored in the accumulator 7 and data D supplied thereto from the data bus. Data A, which is the result of the arithmetic operation performed by the operation circuit 6, is stored in the accumulator 7. The conditions generated during the operation, such as the overflow condition, the plus or minus state of an arithmetic operation result, the "zero" state thereof, a carry output, are represented by respective flags (1-bit signals). The operation circuit 6 arranges these flags in the form of one flag signal F and outputs this flag signal F.
The flag signal F is stored in the flag register 8. Output signal F' from the flag register 8 is supplied to the flag input terminal of the instruction decoder 3 as an operation flag signal.
The instruction decoder 3 uses the operation flag signal F' for determining the branch conditions of a conditional branch instruction. The conditional branch instruction is used for controlling instruction execution procedures.
An example of an operation flag signal F' to which the above condition signals are assigned will be described.
third bit F3' . . . overflow flag V which is "1" at the time of overflow and is "0" in the other situations
second bit F2' . . . sign flag S which is "1" when the result is minus and is "0" in the other situations
first bit F1' . . . zero flag Z which is "1" when the digits of the result are all zero and is "0" in the other situations
zero bit F0' . . . carry flag Z which is "1" when the uppermost digit must be carried and is "0" in the other situations
In order to control the instruction execution procedures in accordance with the flags, conditional branch instructions set forth below are prepared and included in a set of instructions of the processor.
JUMPV LABEL1: if F3'="1", go to address LABEL1
JUMPS LABEL1: if F2'="1", go to address LABEL1
JUMPZ LABEL1: if F1'="1", go to address LABEL1
JUMPC LABEL1: if F0'="1", go to address LABEL1
In general, there may be a case where transfer has to be executed in accordance with the result of an operation. However, the conventional processor cannot use a flag in operations which do not include a carry input or in instructions which are other than branch instructions. Therefore, in order to perform transfer in accordance with the result of an operation, both a transfer instruction and a conditional branch instruction have to be executed. Therefore, even if the processor is so designed as to execute data transfer within one machine cycle, which is a minimum instruction execution time, a task involving data transfer to be executed in accordance with the result of an operation inevitably requires a long time. The time required to complete such a task is twice as long as the time needed to fulfill a task including ordinary data transfer (i.e., unconditional data transfer).
FIGS. 12 and 13 are timing charts showing cases where a conditional branch instruction and a data transfer instruction are executed in combination. In the timing charts, the address signal P output from the program counter 1, the instruction Q stored in the instruction register IR and the data D at the data bus are plotted in relation to time. Symbol "T" represents a machine cycle.
An example of a program corresponding to FIGS. 12 and 13 is as follows:
JUMPV LABEL1+1: when F3'="1", jump to an area which is two addresses ahead
LABEL1:LOAD R0, [100]: transfer data from memory area "100" to register R0.
It is assumed that conditional transfer instruction JUMPV is stored in the n-th address area of the instruction memory and data transfer instruction LOAD is stored in the (n+1)th address area.
The program checks in the first line whether an overflow occurs. If it does occur, the microcomputer jumps to the processing described in the address area which is two addresses ahead, namely, the area identified by "LABEL1+1". In accordance with the second line of the program, data is transferred from the address area "100" of the data memory 4 to the "zero"-ordered register R0 of the register file 5 by way of the data bus.
The timing chart shown in FIG. 12 represents the case where a branch condition is not satisfied.
At time T, the conditional branch instruction or instruction JUMPV described in the first line is read out from the n-th memory area of the instruction memory 2. The readout instruction is written in the instruction register IR.
At time 2T, the JUMPV instruction is executed. Since "F3'=0" is defined in the flag signal F' output from the flag register 8, the branch condition is not satisfied. Accordingly, the instruction decoder 3 does not perform the processing specified in the branch. In the meantime, a LOAD instruction is read out from the (n+1)th address area of the instruction memory 2 and written in the instruction register IR.
Subsequently, the transfer instruction described in the second line is executed at time 3T, and data X is read out from the address area "100" of the data memory 4 and sent to the data bus.
At time 4T, data X sent to the data bus is written in the register R0 of the register file 5.
The timing chart shown in FIG. 12 represents the case where a branch condition is not satisfied.
The timing chart shown in FIG. 13 represents the case where a branch condition is satisfied.
As in the case shown in FIG. 12, the conditional branch instruction or instruction JUMPV described in the first line is read out from the n-th memory area of the instruction memory 2 at time T. The readout instruction is written in the instruction register IR.
At time 2T, the JUMPV instruction is executed. Since "F3'=1" is defined in the flag signal F' output from the flag register 8, the branch condition is satisfied. Accordingly, the instruction decoder 3 performs the processing specified in the branch. In this case, therefore, data X in the address area "100" of the data memory 4 is not sent to the data bus.
Where the branch condition of the JUMPV instruction is satisfied, the instruction decoder 3 supplies control signal k to the instruction memory 2, so that a NOP instruction (no-operation instruction) is output instead of the LOAD instruction. Accordingly, what is stored in the instruction register IR is not the LOAD instruction but the NOP instruction. The NOP instruction is an instruction used for timing adjustment and does not start any kind of operation. Such NOP instructions are prepared in the instruction sets of many types of processors.
The reason for using the NOP instruction in the above process is that the time needed for both the access to the instruction memory 2 and the execution of an instruction by the instruction decoder 3 should be as short as possible. In practice, therefore, the transfer instruction LOAD stored in the (n+1)th address area is read out from the instruction memory 2 and supplied to the instruction register IR, when the instruction decoder 3 is still executing the conditional branch instruction JUMPV.
Simultaneous with the use of the NOP instruction, the instruction decoder 3 supplies control signal j to the program counter 1, thereby causing the program counter 1 to output an address corresponding to a branch. In the example shown in FIGS. 12 and 13, this address is represented by (n+2).
Subsequently, the instruction decoder 3 executes the NOP instruction at time 3T. In addition, the instruction (Qn+2) stored in the address area (n+2) of the instruction memory 2 is written in the instruction register IR.
As described above, the time needed for data transfer is inevitably long if that data transfer is executed in accordance with the result of an operation (the state of an operation flag signal).